1. Field of the Invention
The present invention relates generally to memory cell structures employed within semiconductor products. More particularly, the present invention relates to methods for efficiently fabricating memory cell structures employed within semiconductor products.
2. Description of the Related Art
Common in the semiconductor product fabrication art is the use of memory cell structures, such as dynamic random access memory (DRAM) cell structures, for data storage within semiconductor products. Memory cell structures typically comprise a field effect transistor device as a switching element. One of the source/drain regions within the field effect transistor device typically has electrically connected thereto a capacitor which serves a data storage function. The other of the source/drain regions serves as a connection for a bitline which introduces or extracts charge with respect to the storage capacitor incident to electrical actuation of a wordline which is connected to a gate electrode of the field effect transistor device.
While memory cell structures in general, and dynamic random access memory cell structures in particular, are common in the semiconductor product fabrication art, dynamic random access memory cell structures in particular are not entirely without problems.
In that regard, it is often difficult to fabricate memory cell structures within semiconductor products with enhanced efficiency and enhanced performance.
It is thus towards the foregoing object that the present invention is directed.
Various memory cell structures having desirable properties, and methods for fabrication thereof, have been disclosed in the semiconductor product fabrication art.
Included but not limiting among the memory cell structures and methods for fabrication thereof are those disclosed within: (1) Wang et al., in U.S. Pat. No. 6,362,041 (a method for forming a dynamic random access memory cell structure which employs a contiguous dielectric layer when forming both a gate dielectric layer and a capacitor dielectric layer); and (2) Leung et al., in U.S. Pat. No. 6,468,855 (a reduced topography dynamic random access memory cell structure and method for fabrication thereof).
The teachings of each of the foregoing references is incorporated herein fully by reference.
Desirable in the semiconductor product fabrication art are additional memory cell structures and methods for fabrication thereof, with enhanced efficiency and enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a memory cell structure and a method for fabricating the memory cell structure.
A second object of the invention is to provide a memory cell structure and method for fabrication thereof in accord with the first object of the invention, wherein the memory cell structure is fabricated with enhanced efficiency and enhanced performance.
In accord with the objects of the invention, the invention provides a method for fabricating a memory cell structure.
The method first provides a semiconductor substrate having formed therein an isolation trench adjoining an active region of the semiconductor substrate, where the isolation trench in turn has formed, therein an isolation region. The method also provides for forming within the isolation region an asymmetric trench which exposes a sidewall of the active region. The method further provides for forming into the asymmetric trench a capacitor node layer which contacts the sidewall of the active region. The method next provides for forming upon the active region and the capacitor node layer a contiguous dielectric layer which serves as a gate dielectric layer and a capacitor dielectric layer. The method next provides for forming upon the contiguous dielectric layer a contiguous conductor layer which serves as a gate electrode and a capacitor plate layer. The method next provides for patterning the single conductor layer to form: (1) a gate electrode over the active region of the semiconductor substrate; and (2) a separate capacitor plate layer over the capacitor node layer. Finally, the method provides for forming into the active region a source/drain region electrically connected to the capacitor node layer.
The present invention provides a memory cell structure and a method for fabricating the memory cell structure, wherein the memory cell structure is fabricated with enhanced efficiency and enhanced performance.
The present invention realizes the foregoing object by: (1) fabricating a capacitor within a memory cell structure within an asymmetric trench within an isolation region adjoining an active region of a semiconductor substrate such that a capacitor node layer within the capacitor contacts a sidewall of the active region and is electrically connected with a source/drain region within a field effect transistor device fabricated within the active region of the semiconductor substrate; and (2) employing when fabricating the memory cell structure a contiguous dielectric layer as a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the capacitor.